The present invention relates to a non-volatile memory device. More particularly, the present invention relates to a non-volatile memory device for programming and reading data which reduces errors.
Generally, a flash memory device is divided into a NAND flash memory and a NOR flash memory. In the NOR flash memory, each of the memory cells is connected independently to a bit line and a word line, and so the NOR flash memory has excellent random access time. Whereas, in the NAND flash memory, only one contact is required for one cell string because memory cells are connected in series, and so the NAND flash memory has excellent characteristics for integration. Accordingly, the NAND flash memory has been generally employed in high density flash memory.
Recently, multi bit cells for storing a plurality of data bits in one memory cell has been actively studied so as to enhance the degree of integration of the above flash memory. This memory cell is referred to as a multi level cell (hereinafter, referred to as “MLC”). A memory cell for storing one data bit is referred to as a single level cell (SLC).
The MLC has a plurality of threshold voltage distributions so as to store a plurality of data bits. This means that the data is stored in accordance with each of the cell distribution voltages.
FIG. 1 is a view illustrating a memory cell array in a flash memory device.
In FIG. 1, the memory cell array 110 having memory cells includes a plurality of cell strings.
Each of the cell strings is connected to a corresponding bit line BL. In addition, in each of the cell strings, memory cells C are connected in series between a drain select transistor DST and a source select transistor SST.
Gates of the memory cells are connected to word lines WL.
The memory cell array 110 in FIG. 1 includes a first word line WL<0> to a thirty-second word line WL<31>.
A pair of bit lines is connected to a corresponding page buffer 120. The page buffer 120 may be connected to a different number of bit lines in other implementations.
In the case of programming the thirtieth word line WL<29> of the memory cell array 110, a program voltage is applied to the thirtieth word line WL<29>, and a pass voltage Vpass is provided to the other word lines. Here, since one memory cell stores a plurality of bits in the case that the memory cells C are the MLCs, a threshold voltage of a programmed memory cell in a read operation may be changed based on whether or not memory cells in peripheral cell strings (or adjacent cell strings) of the programmed memory cell are programmed back pattern dependency (BPD).
To reduce the BPD, the word lines WL<0> to WL<31> are programmed sequentially from the first word line WL<0>.
FIG. 2 illustrates a threshold voltage distribution of the memory cells due to BPD. As shown, over-programmed OP memory cells or under-programmed UP memory cells are generated due to the effects of the nearby programmed memory cells, and so the threshold voltage distribution of the memory cells may be widened. In this case, the margin between the threshold voltages of the MLC would be narrowed.
If the pass voltage applied to non-selected word lines is increased too much to reduce the BPD, a disturbance phenomenon of programming unintended memory cells may result.